1. Technical Field
The present invention relates to a memory device for recording two-dimensionally arrayed data including digital image data, a memory controller of the memory device, and a memory system. Particularly, the present invention relates to a memory device, memory controller and memory system for increasing an effective bandwidth indicating the number of data items that can be processed per unit time.
2. Prior Art
The market size of the memory devices for recording two-dimensionally arrayed data, like digital image data, has been gradually increasing along with the popularization of video distribution through digital broadcasting or the Internet. Digital image data is a group of data obtained by constituting gradation information of pixels using a plurality of bits (e.g., 256 gradation levels of 8 bits). For example, one frame of image data for high-definition broadcasting is constituted by 1920×1040 pixels. Each frame of this image data is arranged in an address space within image memory in accordance with a predetermined mapping method.
Such memory mapping is defined so that the most efficient access can be made, on the basis of the configuration and operation of synchronous DRAM (SDRAM) that is presently popular. For example, SDRAM has a plurality of banks, and each bank has a plurality of word lines and bit lines, a plurality of memory cells that are at the intersections of the word lines and bit lines, and sense amplifiers corresponding to the bit lines. The plurality of banks can independently execute active operation. The active operation performed in the SDRAM is a series of operations for selecting a word line and activating the corresponding sense amplifier on the basis of a row address. Further, read operation performed in the SDRAM is a series of operations for outputting a bit-line potential as read data to an input/output terminal on the basis of a column address, the bit-line potential being amplified by the sense amplifier, while write operation is a series of operations for inputting selected write data, which is inputted from the input/output memory, to a bit line that is selected based on the column address.
An address space within a memory of the SDRAM constituted by a plurality of page areas each of which can be selected by a bank address and a row address, and each of the page areas has a group of bits or a group of bytes that can be selected by a column address. The group of bytes (or the group of bits) that are selected by the column address are inputted/outputted via a plurality of input/output terminals.
According to a generally known mapping method, a pixel of digital image data is associated with each byte (or bits) of the group of bytes (or the group of bits) that can be selected by the column address within a page area. Moreover, according to this mapping method, each of the banks of the SDRAM can independently execute the active operation and the read or write operation, thus the plurality of page areas associated with an arrangement of pixels of the digital image data are arranged so that page areas that are vertically and horizontally adjacent to each other on the image correspond to different bank addresses respectively. For example, if the SDRAM is constituted by four banks, the page areas corresponding to bank addresses BA=0, 1 are alternately arranged in the odd-numbered rows, while the page areas corresponding to bank addresses BA=2, 3 are alternately arranged in the even-numbered rows. By arranging the page areas in this manner, when reading or writing one frame of image data, different banks can execute the active operation and the read or write operation alternately and temporally overlapped, and a bandwidth, which is the number of processable pixels per a unit time, can be increased remarkably.
Patent Documents 1 and 2 describe that the access efficiency is improved by allowing simultaneous access to a plurality of rows in a semiconductor memory for storing image data.
Furthermore, Patent Document 3 describes a memory device that is provided with a sub-array selection circuit for performing control to activate, simultaneously, a sub-array allocated to an input row address and a sub-array allocated to a row address right above the input row address, in order to solve the increased reading time and power consumption since the data in every other row need to be read when using the DRAM in image expansion processing. However, Patent Document 3 is designed to enhance the efficiency of horizontal accesses that are made continuously in a row direction of the image, and thus does not describe the rectangular access.
Moreover, Patent Document 4 describes a data processing system in which a bus controller issues an address active command, in response to an access instruction sent from a data processing section, to a storage area different from a storage area accessed in a burst mode, and thereby setting of an access address is made possible. Specifically, while the memory controller activates and accesses one bank, an active command is issued to other bank to perform active operation before hand on this bank, whereby acceleration of read/write operation can be realized.
Also, Patent Document 5 discloses an image processing device having: an image memory; and a control unit for continuously generating a column address while accessing an arbitrary bank, to continuously access an arbitrary address within the same page, and row-activating a bank to be subsequently accessed in advance and thereby immediately accessing the bank to be newly accessed even if accessed bank is switched to another bank. Specifically, there is described that the memory controller has an address order prediction circuit to predict a bank to be subsequently accessed and issue an active command to the memory.
Patent Literature 6 describes a memory system, wherein a volatile memory is provided in a plurality of banks, a refresh target bank is specified by an auto-refresh command, and, during a refresh operation performed by the refresh target bank, the banks other than the refresh target bank execute a normal memory operation in response to a normal memory operation command. However, Patent Literature 6 does not describe that a plurality of refresh counts are set beforehand to perform refresh control.
Patent Literature 7 describes a memory device in which a dual port DRAM is divided into a plurality of banks, and a data read transfer cycle is performed on one bank in synchronization with a refresh cycle performed on other banks.
Patent Literature 8 describes that the memory controller executes access control on the SDRAM with two banks to read and write data, and performs refresh operation by issuing an active command and a pre-charge command to a bank different from the accessed bank.
Patent Literature 9 describes that in the case in which access and refresh are generated simultaneously in a DRAM with two blocks, or in the case in which access has been already generated in one block, an arbiter causes the other block to execute refresh operation, and causes the former block to execute access operation.
[Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2001-312885
[Patent Literature 2] Japanese Unexamined Patent Application Publication No. H08-180675
[Patent Literature 3] Japanese Unexamined Patent Application Publication No. H09-231745
[Patent Literature 4] Japanese Unexamined Patent Application Publication No. 2002-132577
[Patent Literature 5] Japanese Unexamined Patent Application Publication No. H10-105367
[Patent Literature 6] U.S. Patent Application Publication No. US2005/0265104A1
[Patent Literature 7] Japanese Unexamined Patent Application Publication No. H08-115594
[Patent Literature 8] Japanese Unexamined Patent Application Publication No. H09-129882
[Patent Literature 9] Japanese Unexamined Patent Application Publication No. H10-11348
The occurrence of a decrease of the effective bandwidth is not limited in the rectangular access. In a generally-used synchronous DRAM (SDRAM), in response to an auto-refresh command issued from the memory controller, refresh operation is performed in all banks in parallel on the basis of the refresh addresses of the refresh address counters that are commonly provided in the memory. For this reason, once the refresh operation is started, neither horizontal access nor rectangular access can be executed, and the access operation needs to be kept in standby until the refresh operation is ended. As a result, the effective bandwidth decreases.
An object of the present invention, therefore, is to provide a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.